Bi-directional return register stack recovery from...

Bi-level branch target prediction scheme with fetch address pred

Bi-level branch target prediction scheme with mux select predict

Bidirectional communication port for digital signal processor

Bit field extraction with sign or zero extend

Bit field extraction with sign or zero extend

Bit field processor

Bit manipulation instructions

Bit-slice processing unit having M CPU's reading an N-bit width

Block-based branch target buffer

Bossless architecture and digital cell technology for...

Boundary synchronization mechanism for a processor of a...

Branch and return on blocked load or store

Branch control memory

Branch encoding before instruction cache write

Branch history guided instruction/data prefetching

Branch history information writing delay using counter to...

Branch instruction control apparatus and control method

Branch instruction execution control apparatus

Branch instruction for processor with branching dependent on...