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Scheduling instructions with different latencies

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling operations using a dependency matrix

Electrical computers and digital processing systems: processing – Instruction issuing
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Scheduling operations using a dependency matrix

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling program instruction execution by using fence...

Electrical computers and digital processing systems: processing – Processing control
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Scheduling thread upon ready signal set when port transfers...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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Scheme to encode predicted values into an instruction...

Electrical computers and digital processing systems: processing – Processing control
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Scoreboard mechanism for serialized string operations...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Search function for data lookup

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
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Secondary processor execution kernel framework

Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
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Secondary reorder buffer microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Secondary trace build from a cache of translations in a...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Secure execution of program instructions provided by network...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
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Secure hardware personalization service

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
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Security on hardware loops

Electrical computers and digital processing systems: processing – Processing control – Branching
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Segment register renaming in an out of order processor

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
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Segmented pipeline flushing for mispredicted branches

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Select-free dynamic instruction scheduling

Electrical computers and digital processing systems: processing – Instruction issuing
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Selected register decode values for pipeline stage register...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Selecting cache to fetch in multi-level cache system based...

Electrical computers and digital processing systems: processing – Instruction fetching
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Selecting multiple threads for substantially concurrent...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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