Scheduling instructions with different latencies
Scheduling operations using a dependency matrix
Scheduling operations using a dependency matrix
Scheduling program instruction execution by using fence...
Scheduling thread upon ready signal set when port transfers...
Scheme to encode predicted values into an instruction...
Scoreboard mechanism for serialized string operations...
Search function for data lookup
Secondary processor execution kernel framework
Secondary reorder buffer microprocessor
Secondary trace build from a cache of translations in a...
Secure execution of program instructions provided by network...
Secure hardware personalization service
Security on hardware loops
Segment register renaming in an out of order processor
Segmented pipeline flushing for mispredicted branches
Select-free dynamic instruction scheduling
Selected register decode values for pipeline stage register...
Selecting cache to fetch in multi-level cache system based...
Selecting multiple threads for substantially concurrent...