Segmented pipeline flushing for mispredicted branches

Details Segmented pipeline flushing for mispredicted branches Segmented pipeline flushing for mispredicted branches

2007-01-24

2009-11-24

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S239000, C712S217000, C712S218000, C712S219000

Reexamination Certificate

active

07624254

ABSTRACT:
A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

REFERENCES:
patent: 5586278 (1996-12-01), Papworth
patent: 5627985 (1997-05-01), Fetterman
patent: 5812839 (1998-09-01), Hoyt
patent: 0649086 (1995-04-01), None
Akkary et al., Checkpoint Processing and Recovery: Toward Scalable Large Instruction Window Processors, Proceedings of the 36thAnnual IEEE/ACM International Symposium on Microarchitecture, 2003, pp. 423-434.
International Search Report-PCT/US08/051966, International Search Authority-European Patent Office May 20, 2008.
Written Opinion-Pct/Us08/051966, International Search Authority-European Patent Office May 20, 2008.

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