Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1997-09-04
1999-09-14
Moise, Emmanuel L.
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
712216, 712217, 712218, 712219, 712200, G06F 1500
Patent
active
059516704
ABSTRACT:
A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for memory segmentation of the processor. A plurality of physical segment registers are coupled to the logical segment registers. The processor further comprises an issue cluster that issues the instructions and that maps the logical segment registers, specified by the operations, to the physical segment registers to provide segment register renaming in the processor.
REFERENCES:
patent: 5446912 (1995-08-01), Colwell et al.
patent: 5471633 (1995-11-01), Colwell et al.
patent: 5490280 (1996-02-01), Gupta et al.
patent: 5497493 (1996-03-01), Colwell et al.
patent: 5499352 (1996-03-01), Clift et al.
patent: 5517651 (1996-05-01), Huck et al.
patent: 5524262 (1996-06-01), Colwell et al.
patent: 5584038 (1996-12-01), Papworth et al.
patent: 5781753 (1998-07-01), McFarland et al.
Fetterman Michael A.
Glew Andrew F.
Intel Corporation
Moise Emmanuel L.
Pries Catherine M.
LandOfFree
Segment register renaming in an out of order processor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Segment register renaming in an out of order processor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Segment register renaming in an out of order processor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1505816