Segment register renaming in an out of order processor

Electrical computers and digital processing systems: processing – Processing architecture – Superscalar

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Details

712216, 712217, 712218, 712219, 712200, G06F 1500

Patent

active

059516704

ABSTRACT:
A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for memory segmentation of the processor. A plurality of physical segment registers are coupled to the logical segment registers. The processor further comprises an issue cluster that issues the instructions and that maps the logical segment registers, specified by the operations, to the physical segment registers to provide segment register renaming in the processor.

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