Security on hardware loops

Details Security on hardware loops Security on hardware loops

2000-12-28

2004-07-13

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

06763453

ABSTRACT:

BACKGROUND
In designing a programmable processor, such as a digital signal processing (DSP) system, processing speed and power consumption may form tradeoffs. Conventional processors include a variety of hardware designed to increase the speed at which software instructions are executed. The additional hardware, however, typically increases the power consumption of the processor.
A “hardware loop” may increase the speed of a programmable processor. This may be implemented using dedicated hardware designed to expedite the execution of software instructions within a loop construct. Hardware loops may reduce the number of clock cycles used to execute a software loop by caching the instructions in local registers, thereby reducing the need to fetch the same instruction from a memory device or instruction cache a number of times.
Hardware loops introduce several challenges. These challenges include avoiding penalties such as setup penalties or branch penalties. Setup penalties include the loss of performance (usually an increase in processing time) associated with setting up a hardware loop. Similarly, branch penalties are the loss of performance (again, usually an increase in processing time) associated with a branch.


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Lister, A.M.,Fundamentals of Operating Systems, MacMillan Publishers Ltd., London, UK, Third Edition, 1985, pp 28-29.

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