Scheduling instructions with different latencies

Details Scheduling instructions with different latencies Scheduling instructions with different latencies

1998-08-11

2000-03-07

Treat, William M.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712215, 712217, G06F 938

Patent

active

060353899

ABSTRACT:
An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers.

REFERENCES:
patent: 5404469 (1995-04-01), Chung et al.
patent: 5657315 (1997-08-01), Waclawsky
patent: 5745724 (1998-04-01), Favor et al.
patent: 5828868 (1998-10-01), Sager et al.

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