Speculative execution of instructions and processes before...

Speculative generation at address generation stage of...

Speculative hybrid branch direction predictor

Speculative instruction issue in a simultaneously...

Speculative instruction issue in a simultaneously...

Speculative instructions exection in VLIW processors

Speculative issue of instructions under a load miss shadow

Speculative pre-fetching additional line on cache miss if no...

Speculative renaming of data-processor registers

Speculative reuse of code regions

Speculative scheduling of instructions with source operand...

Speculatively scheduling micro-operations after allocation

Split branch system utilizing separate set branch, condition and

Split data-flow scheduling mechanism

Split directory-based cache coherency technique for a...

Split embedded DRAM processor

Split embedded DRAM processor

Split embedded DRAM processor

Split embedded DRAM processor

Split embedded DRAM processor