Split data-flow scheduling mechanism

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

10323337

ABSTRACT:
A scheduling scheme and mechanism for a processor system is disclosed. The scheduling scheme provides a reservation station system that includes a control reservation station and a data reservation station. The reservation station system receives an operational entry and for each operational entry it identifies scheduling state information, operand state information, and operand information. The reservation station system stores the scheduling state information and operand information as a control reservation station entry in the control reservation station and stores the operating state information and the operand information as a data reservation station entry in the data reservation station. When control reservation station entries are identified as ready, they are scheduled and issued for execution by a functional unit. The result from the functional unit is distributed within the control reservation station and the data reservation station for subsequent operational entries to use in preparation for scheduling and issuing those entries for execution.

REFERENCES:
patent: 5951670 (1999-09-01), Glew et al.
patent: 6070235 (2000-05-01), Cheong et al.
patent: 6122721 (2000-09-01), Goddard et al.
patent: 6292884 (2001-09-01), Tran et al.
patent: 6311267 (2001-10-01), Nguyen et al.
patent: 6351804 (2002-02-01), Pflum
patent: 6542986 (2003-04-01), White
patent: 6643767 (2003-11-01), Sato
patent: 6742111 (2004-05-01), Soni
Mahlke, Scott A. et al, “A Comparison of Full and Partial Predicated Execution Support for ILP Processors,” ISCA-22, Jun. 1995, 12 pages.
“PC Processor Microarchitecture,” ExtremeTech, retrieved Dec. 19, 2001, <http://www.extremetech.com/article0,3396,apn%3D17%26s%3D1598%26a%3>, 4 pages.
“Understanding the Intel P6 Microarchitecture,” Chipcenter, retrieved Dec. 19, 2001 <http://www.chipcenter.com/eexpert/code-opt/dgilbertC001:html?PRINIT=true>.
Moudgill, Mayan, “Precise Interrupts,” IEEE Micro, Feb. 1996, pp. 58-67.
Gilbert, David, “Microprocessor Functional Unit Series, Part 4: Branch Unit,” retrieved Dec. 19, 2001, <http://www.chipcenter.com/eexpert/dgilbert/dgilbert033.html?PRINT=true>.
Wang, Dazhi and Zhang, Jing, “Develop dynamically scheduled processor model using ATOM,” Duke University, Dec. 10, 2000, 12 pages.
“Petnium® Pro Processor Technical Glossary,” 2 pages.
Intel Corporation, “A Tour of the Pentium® Pro Processor Microarchitecture,” Oct. 1995.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Split data-flow scheduling mechanism does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Split data-flow scheduling mechanism, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Split data-flow scheduling mechanism will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3880833

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.