Speculative execution of instructions and processes before...

Electrical computers and digital processing systems: processing – Processing control – Processing sequence control

Reexamination Certificate

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C712S235000

Reexamination Certificate

active

06880073

ABSTRACT:
Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are speculatively executed before the barrier operation completes on the system bus. The processor comprises a load/store unit (LSU) with a barrier operation (BOP) controller that permits load instructions subsequent to syncs in an instruction sequence to be speculatively issued prior to the return of the sync acknowledgment. Data returned is immediately forwarded to the processor's execution units. The returned data and results of subsequent operations are held temporarily in rename registers. A multiprocessor speculation flag is set in the corresponding rename registers to indicate that the value is “barrier” speculative. When a barrier acknowledge is received by the BOP controller, the flag(s) of the corresponding rename register(s) are reset.

REFERENCES:
patent: 5615350 (1997-03-01), Hesson et al.
patent: 5822575 (1998-10-01), Tran
patent: 6216200 (2001-04-01), Yeager
patent: 6286095 (2001-09-01), Morris et al.
patent: 6415380 (2002-07-01), Sato
patent: 6606702 (2003-08-01), Guthrie et al.

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