Speculative issue of instructions under a load miss shadow

Details Speculative issue of instructions under a load miss shadow Speculative issue of instructions under a load miss shadow

1998-04-10

2000-08-01

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712215, 712225, 714 48, G06F 9312

Patent

active

060981660

ABSTRACT:
A technique for speculatively issuing instructions using an out-of-order processor. A cache miss by a load instruction results in either a reissue of all subsequently issued instructions for an integer instruction stream, or a reissue of only truly dependent instructions for a floating point instruction stream. One version of the technique involves issuing and executing a first instruction, and issuing a second instruction during a speculative time window of the first instruction that occurs after the first instruction is issued. The technique further involves executing the issued second instruction when the first instruction is executed in a first manner, and reissuing the second instruction and executing the reissued second instruction when the first instruction is executed in a second manner that is different than the first manner.

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