Power reduction mechanism for floating point register file...

Power saving methods and apparatus to selectively enable...

Power saving methods and apparatus to selectively enable...

Power-and speed-efficient data storage/transfer architecture...

Pre-arbitrated bypasssing in a speculative execution...

Pre-decode checking for pre-decoded instructions that cross...

Pre-decoding variable length instructions

Pre-fetch apparatus

Pre-loading context states by inactive hardware thread in...

Pre-prefetching target of following branch instruction based...

Pre-steering register renamed instructions to execution unit...

Pre-tracing instructions for CGA coupled processor in...

Precise counter hardware for microcode loops

Precoding branch instructions to reduce branch-penalty in...

Predecode buffer including buffer pointer indicating another...

Predecoding and steering mechanism for instructions in a supersc

Predecoding multiple instructions as one combined...

Predecoding technique for indicating locations of opcode bytes i

Predicate controlled software pipelined loop processing with...

Predicate prediction based on a predicated predicate value