Precise counter hardware for microcode loops

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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Reexamination Certificate

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07937574

ABSTRACT:
In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coupled to the microcode memory, the sequence control unit is configured to control reading microcode operations from the microcode memory to be issued for execution by the processor. The sequence control unit is configured to stall issuance of microcode operations forming a body of a loop in a first routine of the plurality of microcode routines until a loop counter value that indicates a number of iterations of the loop is received by the sequence control unit.

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Patterson, David. Hennessy, John. “Computer Architecture: A Quantitative Approach”. Morgan Kaufmann Publishers, Inc. Second Edition, 1996. pp. 161-169.
Mayer, Herb. “Loop Instruction in x86”. Mar. 17, 2003. 5 pages.

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