Pre-tracing instructions for CGA coupled processor in...

Details Pre-tracing instructions for CGA coupled processor in... Pre-tracing instructions for CGA coupled processor in...

2008-03-05

2010-11-16

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction fetching

Prefetching

C712S043000

Reexamination Certificate

active

07836277

ABSTRACT:
A method of managing an instruction cache and a process of using the method are provided. The processor may comprise a processor core which is operated either during an active mode or during an inactive mode wherein the process core performs at least one instruction during the active mode, an instruction cache which pre-traces a first instruction and determines, during the inactive mode, whether the processor core will meet a cache miss with regard to the first instruction, wherein the first instruction is to be performed by the processor core during the active mode, a coarse-grained array which performs a second instruction during the inactive mode, and a configuration memory which stores configuration information of the coarse-grained array, wherein the coarse-grained array performs the second instruction using the configuration information.

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