Memory accelerator with two instruction set fetch path to...
Memory access address comparison of load and store queques
Memory access consolidation for SIMD processing elements...
Memory controller having front end and back end channels for...
Memory disambiguation scheme for partially redundant load...
Memory organization allowing single cycle pointer addressing...
Memory request / grant daemons in virtual nodes for moving...
Memory request protocol method
Memory shared between processing threads
Memory store from a register pair conditional upon a selected st
Memory system for ordering load and store instructions in a...
Merge microinstruction for minimizing source dependencies in...
Merged array controller and processing element
Merged control/process element processor for executing VLIW...
Merged control/process element processor for executing VLIW...
Merging branch information with sync points
Merging narrow register for resolution of data dependencies...
Merging single precision floating point operands
Mesh connected computed
Mesh connected computer