Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2011-05-03
2011-05-03
Fennema, Robert (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Reexamination Certificate
active
07937561
ABSTRACT:
A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstruction that specifies an N-bit first source register, an 8-bit second source register, and an N-bit destination register to receive an N-bit result. The N-bit first source register and the N-bit destination register are the N-bit architected general purpose register. An execution unit receives the merge microinstruction and responsively generates the N-bit result to be subsequently written to the N-bit architected general purpose register even though the macroinstruction only instructs the microprocessor to write the 8-bit result into the lower 8 bits of the N-bit architected general purpose register. Specifically, the execution unit directs the 8-bit result into the lower 8 bits of the N-bit result and directs the upper N-8 bits of the N-bit first source register into corresponding upper N-8 bits of the N-bit result.
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Col Gerard M.
Parks Terry
Davis E. Alan
Fennema Robert
Huffman James W.
VIA Technologies Inc.
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