Electrical computers and digital processing systems: processing – Instruction fetching
Reexamination Certificate
2007-10-30
2007-10-30
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction fetching
C711S167000, C712S207000
Reexamination Certificate
active
10923284
ABSTRACT:
A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.
REFERENCES:
patent: 4438493 (1984-03-01), Cushing et al.
patent: 4755933 (1988-07-01), Teshima et al.
patent: 5634025 (1997-05-01), Breternitz, Jr.
patent: 5659713 (1997-08-01), Goodwin et al.
patent: 6643755 (2003-11-01), Goodhue et al.
patent: 0180236 (1986-05-01), None
Goodhue Gregory K.
Kallal Robert Michael
Khan Ata R.
Wharton John H.
Kim Kenneth S.
NXP B.V.
Zawilski Peter
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