Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2000-05-02
2004-03-02
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S218000
Reexamination Certificate
active
06701425
ABSTRACT:
The invention relates to apparatus and methods for accessing memory in a computer system and particularly for comparing load and store addresses.
BACKGROUND OF THE INVENTION
Computer systems may comprise a plurality of parallel execution pipelines used to generate access addresses for load and store operations in a memory as well as data for storing in the memory. Where more than one pipeline is used, instructions may pass through the pipelines at different rates so that data and addresses from the different pipelines may arrive at a memory access unit at different times. Addresses and data may be put onto queues for use in memory access operations.
It is an object of the present invention to provide improved apparatus and methods for handling load and store queues in accessing a computer data memory.
SUMMARY OF THE INVENTION
The invention provides a computer system having a memory, a plurality of parallel execution pipelines and a memory access controller, said access controller providing a plurality of queues including store address queues holding addresses for store operations to be effected in the memory, store data queues holding a plurality of data for storing in the memory at locations identified by the store address queues, and load address storage holding addresses for load operations to be effected from the memory, said access controller including comparator circuitry to compare load addresses received by the controller with addresses in the store address queue and locate any addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits and said comparator having circuitry to compare the byte enable bits of two addresses as well as said first set of bits.
Preferably said memory includes two separately accessible memory banks, each bank storing half a word at each word address.
Preferably said byte enable signals indicate which byte positions at each word address are to be accessed.
Preferably said comparator comprises a plurality of comparator devices, two of which effect comparison of addresses in respective memory banks, each of said two comparator devices having first inputs for comparing the bank word addresses for a pair of load and store addresses and second inputs for comparing respective byte enable signals of a pair of load and store addresses.
Preferably control circuitry is provided to select memory access operations from said queues, said control circuitry being responsive to the output of said comparator circuitry to select a load operation before a store address operation if the comparator circuitry does not indicate a store operation at the same address as the load operation.
Preferably said control circuitry is operable to select store operations before load operations when said comparator circuitry outputs a hit signal to indicate the same address on a store address queue as a received load address.
Preferably said control circuitry includes hit flag circuitry responsive to execution of an instruction to effect all current store operations in the store address queue before executing any further load operations, said hit flag being set in response to execution of said instruction.
Preferably said hit flag is operable when set to provide to the control circuitry the same input as said comparator circuitry when the comparator outputs a hit signal to indicate the same address on a store address queue as a received load address.
Preferably said plurality of execution pipelines include one or more pipelines in a data unit arranged to execute arithmetic operations and one or more pipelines in an address unit arranged to execute memory addressing operations.
Preferably at least two parallel pipelines are provided in the data unit and at least two parallel pipelines are provided in the address unit.
Preferably said memory includes two or more memory regions having different mapping within the addressable memory space of the computer system, said comparator circuitry including comparator means to compare the mapping of load addresses with each entry in the store address queues as well as comparing the word address and the byte enable signals.
The invention includes a method of operating a computer system having a memory, a plurality of parallel execution pipelines and a memory access controller, said method comprising forming a plurality of queues including store address queues holding addresses for store operations to be effected in the memory, store data queues holding a plurality of data for storing in the memory at locations identified by the store address queue and load address storage holding addresses for load operations to be effected from the memory, said method further comprising comparing received load addresses with addresses in a store address queue to locate addresses which are the same, each of said addresses including a first set of bits representing a word address together with a second set of byte enable bits, the comparison including comparing the byte enable bits of the two addresses as well as comparing said first set of bits.
Preferably, store addresses are removed from the store address queue in accordance with the order of entries in the queue and said comparison of addresses compares the next load address with all entries in the store address queue.
Preferably data is stored in said memory in two separately addressable memory banks sharing common addresses, each bank storing half a word at each word address, said comparison being effected by comparing bank word addresses in two comparison devices each for a respective bank and each for saving the same bank word address, and comparing in a further comparison device byte enable signals which represent respectively byte enable signals for the two different banks.
The method may include executing an instruction to set a hit flag indicating that all current store addresses in the store address queue should be accessed for a store operation before executing any further load operation.
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European Search Report from European application No. 99410056, filed May 3, 1999.
Bernard Bruno
Dabbagh Ahmed
Grossier Nicolas
Taloud Pierre-Yves
Morris James H.
STMicroelectronics S.A.
Tsai Henry W. H.
Wolf Greenfield & Sacks P.C.
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