Processor configured to selectively free physical registers...
Processor core and method for managing program counter...
Processor employing multiple register sets to eliminate interrup
Processor executing unpack instruction to interleave data...
Processor for improving instruction utilization using...
Processor for performing subword permutations and combinations
Processor for processing a program with commands including a...
Processor having a conditional branch extension of an...
Processor having a dedicated hash unit integrated within
Processor having a hierarchical control register file and method
Processor having data buffer for speculative loads
Processor having efficient function estimate instructions
Processor having efficient function estimate instructions
Processor having multiple program counters and trace buffers...
Processor having multiple program counters and trace buffers...
Processor having multiple program counters and trace buffers...
Processor having selectable exception handling modes
Processor having selective branch prediction
Processor including a combined parallel debug and trace port...
Processor including fallback branch prediction mechanism for...