Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1999-03-22
2001-11-20
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S235000
Reexamination Certificate
active
06321328
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to central processor architecture and, more particularly, to techniques for improving the performance of central processors which execute speculative load instructions.
BACKGROUND OF THE INVENTION
One of the key goals in the design of computers is to reduce the latency involved in memory access. Generally, central processing unit (CPU) speeds have increased faster than memory access time, thereby exacerbating the problem. Thus a memory access operation may require multiple CPU cycles, and the processor may be stalled while waiting for data to execute the next instruction. Unless steps are taken to reduce memory latency and its effects, the benefits of high speed processors are not achieved.
In addition to design improvements which reduce memory latency per se, computer architectures typically have features which limit the effects of memory latency. One common approach to reducing the effects of memory latency is to utilize a cache memory. The cache is a relatively small, low latency memory that contains data required by instructions currently being executed. When a load instruction is executed, main memory is accessed and a block of data containing the required data word is placed in the cache. Typically that block of data remains in the cache until it is replaced by another block that needs the space. On subsequent accesses to the same data block, the data is read from the cache with low latency. The success of the cache depends on the fact that computer programs typically require multiple accesses to the same data block within a short time and on the fact that the cache has substantially lower latency than the main memory. The performance of caches may be optimized with respect to capacity, replacement algorithms and the like. Both data caches and instruction caches have been utilized.
Another way to reduce the effects of memory latency is to execute load instructions out of order in the instruction sequence. More particularly, the load instruction is moved earlier in the instruction sequence, so that the accessed data will be available to the execution unit by the time it is needed. As a result, delay caused by memory latency is avoided.
However, when the load instruction is moved earlier in the instruction sequence, it is likely to be executed speculatively, because the compiler does not know if one or more subsequent branch instructions will take a path away from the load instruction. Unfortunately, data blocks accessed as part of a speculative load instruction that is never needed will displace data in the cache that may be needed later. A delay may be incurred in reloading the displaced data when it is needed. Thus, loading of data into the cache in response to a speculative load instruction may have an adverse effect on performance, despite the fact that the speculative data is not used.
Accordingly there is a need for improved computer apparatus and methods of operation wherein the adverse effects of memory latency are reduced.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, computer apparatus is provided. The computer apparatus comprises an execution unit for executing a sequence of instructions which may include a speculative load instruction, a memory for storing data required by the instructions for execution, a low latency data cache for holding data accessed in the memory in response to the instructions, a low latency data buffer for holding speculative data accessed in the memory in response to the speculative load instruction, and a controller. The controller loads the speculative data from the memory into the data buffer in response to the speculative load instruction when the speculative data is not present in the data buffer or the data cache, and loads the speculative data from the data buffer into the execution unit. The speculative data may be loaded from the data buffer into the execution unit when the speculative load instruction is executed or when the speculative load instruction is committed. The speculative data is supplied to the execution unit with low latency and without contamination of the data cache.
In a first embodiment, the controller further comprises means for transferring the speculative data from the data buffer to the data cache when the speculative load instruction is committed. In a second embodiment, the controller further comprises means for retaining the speculative data in the data buffer when the speculative load instruction is committed. In either case, the speculative data is provided to the execution unit with low latency. If the speculative data is not needed, it is eventually replaced in the data buffer, without having contaminated the data cache. In the event that the data is transferred from the data buffer to the data cache after the speculative load instruction is committed, the data is no longer speculative and therefore does not contaminate the data cache.
The controller may further comprise means for replacing data in the data buffer with the speculative data when data is loaded from the memory into the data buffer and space is not available in the data buffer. Any suitable replacement algorithm may be used. The data buffer preferably has a fully-associative architecture. Typically, the data cache has a larger capacity than the data buffer.
According to another aspect of the invention a method is provided for executing instructions in a computer apparatus comprising an execution unit, a memory and a low latency data cache. The method comprises the steps of supplying to the execution unit a sequence of instructions which may include a speculative load instruction, storing in the memory data required by the instructions for execution, and holding in the data cache data accessed in the memory in response to the instructions. The method further comprises providing the computer apparatus with a low latency data buffer. Speculative data required by the speculative load instruction is loaded from the memory into the data buffer when the speculative data is not present in the data buffer or the data cache, and is loaded from the data buffer into the execution unit, either when the speculative load instruction is executed or when the speculative load instruction is committed.
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Gupta Rajiv
Karp Alan H.
Coleman Eric
Hewlett--Packard Company
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