Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Patent
1998-12-04
2000-11-28
Treat, William M.
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
712244, 710260, G06F 9312
Patent
active
061548324
ABSTRACT:
A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other (non-interrupt) tasks. The interrupt sources may record interrupt service requests instead of signalling an interrupt to the processor. Periodically, the processor may poll the interrupt sources to determine if a service request is recorded.
REFERENCES:
patent: 4905190 (1990-02-01), Yokoyama
patent: 5050067 (1991-09-01), McLagan et al.
patent: 5421014 (1995-05-01), Bucher
patent: 5515538 (1996-05-01), Kleiman
patent: 5546593 (1996-08-01), Kimura et al.
patent: 5649225 (1997-07-01), White et al.
patent: 5724565 (1998-03-01), Dubey et al.
Elkateeb et al., "An Evaluation to the Use of the Non-Overlapped Multiple Register Sets in the Network Nodes Processor", 1997 IEEE Pacific Rim Conference on Communications, Computers, and Signal Processing, 1997.10 Years PACRIM 1987-1997-Networking the Pacific Rim, vol. 2, pp. 887-890.
Elkateeb, "The Impact of Using RISC Architecture in the Network Nodes Processor", Intelligent Information Systems, IIS '97 Proceedings, pp. 540-544, 1997.
Hiroaki et al, "An Elementary Processor Architecture With Simultaneous Instruction Issuing From Multiple Threads," Computer Architecture News, vol. 20, No. 2, May 1, 1992, pp. 136-145.
"Register Banking for IBM System/370," IBM Technical Disclosure Bulletin, vol. 34, No. 4B, Sep. 1, 1991, pp. 372-373.
Byrd et al, "Multithreaded Processor Architectures," vol. 32, No. 8, Aug. 1995, New York US, pp. 38-46.
Intel Corp., "MultiProcessor Specification," Version 1.1, Apr. 1994, pp. 1,1-Glossary 2.
Hummel, "PC Magazine Programmer's Technical Reference: the Processor and Coprocessor", 1992, pp. 153-182.
Intel Corp., "Microprocessor & Peripheral Handbook--Vol. I Microprocessor," 1989, pp. 2-259 through 2-277.
Singh, et al., "16-Bit and 32-Bit Microprocessors Architecture, Software, and Interfacing Techniques," 1991, pp. 302-305.
Advanced Micro Devices , Inc.
Merkel Lawrence J.
Treat William M.
LandOfFree
Processor employing multiple register sets to eliminate interrup does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Processor employing multiple register sets to eliminate interrup, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor employing multiple register sets to eliminate interrup will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1735954