Globally observing load operations prior to fence...

Details Globally observing load operations prior to fence... Globally observing load operations prior to fence...

2007-07-24

2007-07-24

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C711S141000, C712S216000

Reexamination Certificate

active

10778512

ABSTRACT:
A system includes a memory unit and a processor where the processor has a load buffer to store a first instruction and a cache controller to block the first instruction from dispatch into the cache controller until load data for load operations prior to the first instruction fetched from the memory unit are globally observed. The processor further may include a control register having a first mode storage to store a mode control selection for pre-serialization and a second mode storage to store a mode control selection for post-serialization to enable control of pre-serialization and post-serialization of load operations with respect to the first instruction. Other embodiments are described and claimed.

REFERENCES:
patent: 5745729 (1998-04-01), Greenley et al.
patent: 5748937 (1998-05-01), Abramson et al.
patent: 6073210 (2000-06-01), Palanca et al.
patent: 6223258 (2001-04-01), Palanca et al.
patent: 6609192 (2003-08-01), Guthrie et al.
patent: 6651151 (2003-11-01), Palanca et al.

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