Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
2001-02-13
2004-12-14
Kim, Kenneth S. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C712S208000, C712S214000
Reexamination Certificate
active
06832309
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a command processing device that performs a predetermined processing based on a command stored in a memory device. The present invention also relates to a method for processing a command.
This application is a counterpart of Japanese patent application Serial Number 39802/2000, filed Feb. 14, 2000, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
In a command processing device, one command is processed by two or more following states. First, a command code (hereinafter “command”) is fetched from an external memory device, such as a ROM. Next, the command is decoded. Then, the decoded command is executed. In a state by which the command is executed, a write-in operation of the command to a command register, etc. is contained. There is a technology that improves a performance of the command processing device performing the above state. The technology is referred to as command fetch pipeline processing (hereinafter “pipeline processing”). In the pipeline processing, a plurality of commands are divided into the states, thus the commands are processed in parallel. According to pipeline processing, it is possible to shorten the time required in order to perform a program.
One example of the conventional command processing device
300
, which performs the above mentioned pipeline processing, is explained with referring to FIG.
18
. One command in this command processing device
300
is processed by passing through a state (IF state) in which a command is fetched, a state (ID state) in which the fetched command is decoded, and a state (EX state) in which the decoded command is executed and written in a register. In addition, the command which the above three states comprised of and ends within one machine cycle is referred to as the minimum execution cycle command.
As shown in
FIG. 18
, the command processing device
300
is made up of an IF state part
310
, an ID state part
320
, and an EX state part
330
.
The IF state part
310
includes a memory device
311
, a control device
312
which designates an address location in the memory device
311
, an incrementor
313
, a selector
314
which is connected to the incrementor
313
and an Arithmetic and Logic Unit
331
(it is called ALU hereinafter) explained later and which selects either an output of the ALU
331
or an output of the incrementor
313
, and a command storing register
315
.
The ID state part
32
includes a command decoded
321
which is comprised of a logic circuit and which decodes an execution command stored in the command storing register
315
, a register file
322
which stores an operation result and the object an “operand”) of operation, a RAM
323
which stores an operation result and an operand, a selector
324
which selects either an output of the register file
322
or an output of the RAM
323
, a storing register
325
which feeds back an operand to be performed, and an address register
326
which feeds back an output of the storing register
325
to the RAM
323
. The command decoder
321
outputs a control signal for executing a command to the register file
322
and the address register
326
.
The EX state part
330
is constituted by the ALU
331
. The ALU
331
inputs a command and an operand from the storing register (not illustrated) in the ID state part
320
and performs a predetermined operation. Then, the ALU
331
outputs the operation result to the register file
322
and the RAM
323
in the II) state part
320
and controls the selector
314
in the IF state part
310
.
As mentioned above, each state of the command is processed by the corresponding structure element in the command processing device
300
. According to the above structure, while one state under one command is performed, another state under another command can be performed. That is, it is enabled to perform pipeline processing.
FIG. 19
is a timing chart showing a processing time when the pipeline processing with respect to commands
1
through
4
, wherein each of the commands is the minimum execution cycle command, are executed. For example, at the processing time t, the EX state of the command
1
, the ID state of the command
2
, and the IF state of the command
3
are simultaneously performed. As mentioned above, by dividing commands into states, parallel processing of two or more commands can be carried out. Thus, commands are processed in parallel. According to the pipeline processing, it is possible to shorten the whole processing time.
By the way, in order to shorten the whole processing time in the above mentioned pipeline processing, the time of each state needs to be made as short as possible and equal. That is, when one state is very long compared with another state, the whole processing time depends on the processing time of the one state. As a result, the original purpose of shortening the time required for executing a program can not be obtained.
As architecture of the command processing device generally used, there are RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer). These have the following features. That is, in RISC, while there is an advantage that command decoding time and command execution time are short because each command is simple, there is a disadvantage that command read out time is long.
In CICS, although there is an advantage that command read out time is short because CISC includes the complicated command decoding mechanism, there is a disadvantage that command decoding time and command execution time are long. Thus, from the viewpoint of equalization of the processing time of each state, neither RISC nor CISC is suitable architecture. Consequently, there has been a need for a new architecture having each advantage.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a command processing device that can execute a command efficiently.
It is still another object of the present invention is to provide a command processing device having a simplified structure.
It is still another object of the present invention is to provide a command processing device having a smaller circuit area.
It is still another object of the present invention is to provide a method for processing command that can improve a processing time.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a command processing device that includes
a first command storing circuit which stores a command and a decode circuit which decodes the command from the first command storing circuit and which outputs a decoded command and a control signal. The device also includes a command generating circuit which receives the command from the first command storing circuit, which generates a command in response to the control signal, and which outputs generated command to the decode circuit.
According to another aspect of the present invention, for achieving one or more of the above objects, there is provided a method for processing command that includes the following steps. That is, the method includes generating a first command composed of a plurality of bits; decoding the first command; executing a predetermined process based on the decoded first command; generating a second command by using the first command based on the decoded result of the first command; decoding the second command; and executing a predetermined process based on the decoded second command.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 4831572 (1989-05-01), Sekiguchi
patent: 6434690 (2002-08-01), Ohsuga et al.
Kim Kenneth S.
Nixon & Peabody LLP
Oki Electric Industry Co. Ltd.
Studebaker Donald R.
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