Multimedia instruction set for wide data paths

Multithreaded microprocessor with asymmetrical central...

Multithreaded processor for processing multiple instruction stre

Optimized allocation of multi-pipeline executable and...

Optimum power efficient shifting algorithm for schedulers

Partitioned issue queue and allocation strategy

Pipe scheduling for pipelines based on destination register...

Pipelined instruction dispatch unit in a superscalar processor

Pipelined instruction dispatch unit in a superscalar processor

Pre-steering register renamed instructions to execution unit...

Predecoding and steering mechanism for instructions in a supersc

Preventing the execution of a set of instructions in...

Processor

Processor

Processor architecture including grouping circuit

Processor for making more efficient use of idling components...

Processor to execute in parallel plurality of instructions...

Recorder buffer and a method for allocating a fixed amount of st

Register access scheduling method for multi-bank register...

Reorder buffer configured to allocate storage for...