Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
1999-07-28
2003-04-15
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C709S241000
Reexamination Certificate
active
06550000
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a processor to execute in parallel a plurality of instructions using a plurality of functional units, and an instruction allocation controller. Particularly, the present invention relates to a processor in which the VLIW (very-long-instruction-word) system that executes in parallel a plurality of instructions at the same time using a plurality of functional units is applied, and an instruction allocation controller.
2. Description of the Background Art
When a single instruction is executed by a microprocessor, the register in which the operation result is to be stored is specified, and the content of the special register called the flag register is modified, if necessary. The VLIW and superscaler type CPU architectures which have been recently developed are directed to execute instructions in parallel. When a plurality of instructions are to be executed at the same time by the superscaler, the task of allocating each instruction to an appropriate one of the functional unit must be carried out every time. In contrast, since a functional unit in which an instruction is executed is determined on creating a program for a VLIW type processor among a plurality of functional units, the hardware for such a processor can be reduced compared to the one employing superscaler architecture.
Although the microprocessor in which the VLIW is applied can execute a plurality of instructions simultaneously by including a plurality of functional units, it sometimes happens when a flag register is to updated by a plurality of instructions executed in parallel. This is referred to as “conflict”. Such a conflict is not preferable since execution of the program will look as if it has stopped when such a conflict occurs. In order to avoid this conflict state, the executing order of the instructions must be scheduled in advance so that a plurality of instructions that will update the content of the flag register are not executed simultaneously. This leads to a decreased number of instructions that are executed in parallel, which means degrading the throughput. There is also the problem that the program is increased m size.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a processor and an instruction allocation controller that can improve the throughput.
Another object of the present invention is to provide a processor and an instruction allocation controller that can reduce the size of the program to be executed.
According to an aspect of the present invention, a processor includes a plurality of functional units. When a plurality of instructions in the program are executed in parallel using a plurality of functional units, determination is made in advance of which of the plurality of functional units is used for execution of respective instructions.
The processor includes a register in which control information that is shared by the plurality of functional units for program execution control is stored and accessed in common by the plurality of functional units, and an arbitration unit arbitrating access according to predetermined priority of control information access among the plurality of functional units when the content of the register is to be simultaneously accessed by the plurality of functional units in the parallel execution of a plurality of instructions.
When simultaneous access of the control information in the register is attempted by a plurality of functional units in program execution in the processor, the access from only one functional unit is made valid by the arbitration unit according to the predetermined priority. As a result, a conflict among the plurality of functional units as to the control information in the register can be avoided.
Since the execution order of instructions does not have to be scheduled to avoid a conflict of access of control information among the plurality of functional units, the number of instructions that can be substantially executed at the same time can be increased than the conventional case. More specifically, the substantial throughput becomes higher, and the size of the program is reduced.
In the register of the processor of the present aspect, control information provided individually for each of the plurality of functional units associated with execution control of the program are also stored.
The arbitration unit includes a first arbitration unit selectively setting a share mode in which the access of shared control information is arbitrated according to the predetermined priority among the plurality of functional units and a discrete mode in which respective individual control information is accessed by a corresponding functional unit when the plurality of functional units attempt to access simultaneously the content of the register in parallel execution of a plurality of instructions.
Therefore, when the content of the register is to be accessed simultaneously by a plurality of functional units in the parallel execution of a plurality of instructions and the share mode is set at the first arbitration unit, the shared control information in the register is accessed according to the predetermined priority among the plurality of functional units. Only the access from one functional unit is enabled. A conflict among the plurality of functional units regarding access of the shared control information is avoided. When the first arbitration unit is set to the discrete mode, each of the plurality of functional units accesses the individual corresponding discrete control information in respective registers. Therefore, a conflict among the plurality of functional units accessing simultaneously the content of the register can be avoided.
Thus, scheduling the execution order of the instructions to avoid such a conflict is no longer required. As a result, the number of instructions that can be substantially executed at the same time increases. In other words, the substantial throughput increases and the size of the program is reduced.
In the processor of the present aspect, either the share mode or the discrete mode is selectively set according to the feature of the program. Therefore, the operational ability can be improved in the mode corresponding to the feature of the program. Also, the specification of the program can be made more versatile.
In the processor of the present aspect, the plurality of instructions include an instruction of designating simultaneously a predetermined operation on a high order half-word and a predetermined operation on a low order half-word. The control information includes at least one flag to indicate the state of a relevant predetermined operation for respective predetermined operations on the high order and low order half-words.
Therefore, the flag to indicate the state of each predetermined operation when a predetermined operation is executed for each half-word by one instruction can be retained in the register. Thus, a conflict among the plurality of functional units can be avoided even when the instruction designating simultaneous predetermined operation on the high order half-word and low order half-word is executed in any of the plurality of functional units in the processor. Such an instruction can be used in a wider application. The development tool of the software can be made more versatile.
In the processor of the present aspect, determination of which of the plurality of functional units is used to execute respective plurality of instructions is made at the stage of assembling the program.
In the present aspect, the processor further includes a particular functional unit differing from the plurality of functional units. The particular functional unit applies a predetermined operation on the control information and writes the value of the result into the register as control information.
Thus, the particular functional unit applies a predetermined operation on the control information that is accessed by a plurality of functional units and writes the resulting value into the register as the control in
Minematsu Isao
Yamada Akira
Coleman Eric
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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