Register access scheduling method for multi-bank register...

Details Register access scheduling method for multi-bank register... Register access scheduling method for multi-bank register...

2007-02-13

2007-02-13

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

Reexamination Certificate

active

10370172

ABSTRACT:
A parallel processor has a plurality of operation units that execute operation instructions, and a multi-bank register file in which a plurality of banks each having a plurality of registers are formed. Each of machine instructions, which are input simultaneously, is split into a plurality of nano-instructions each of which includes at least one of an access instruction and operation instruction. The output clock cycles of operation instructions with respect to the operation units are arbitrated. Furthermore, the output clock cycles of access instructions to the multi-bank register file are arbitrated so as to prevent access instructions from contending in an identical bank in the multi-bank register file.

REFERENCES:
patent: 6742111 (2004-05-01), Soni
patent: 6938149 (2005-08-01), Kunimatsu et al.
Mattausch, H.J., “Hierarchical Architecture for Area-Efficient IntegratedN-Port Memories With Latency-Free Multi-Gigabit Per Second Access Bandwidth,”Electronics Letters 35(17):1-2, 1999.
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Mattausch, H.J., et al., “Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage With High Random-Access Bandwidth and Large Storage Capacity,”IEICE Transactions on Electronics E84-C(3):410-417, 2001.
Tatsumi, Y., and H.J. Mattausch, “Fast Quadratic Increase of Multiport-Storage-Cell Area With Port Number,”Electronics Letters 35(25):1-2, 1999.

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