Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent
1997-08-27
2000-08-15
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
712205, 712206, 712208, 712212, 712216, 712 23, G06F 938
Patent
active
061051276
ABSTRACT:
A multithreaded processor for executing multiple instruction streams is provided. This multithreaded processor includes: a plurality of functional units for executing instructions; a plurality of instruction decode units, corresponding to the multiple instruction streams on a one-to-one basis, for respectively decoding an instruction, and producing an instruction issue request for designating to which functional unit the decoded instruction should be issued and requesting for the issuance of the decoded instruction to the designated functional unit; a holding unit for holding the priority level of each instruction stream; and a control unit for deciding which decoded instruction should be issued to a functional unit designated by two or more instruction issue requests at the same time, in accordance with the priority levels held by the holding unit.
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Kimura Kozo
Kiyohara Tokuzo
Yoshioka Kousuke
An Meng-Ai T.
El-Hady Nabil
Matsushita Electric - Industrial Co., Ltd.
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