Processor architecture including grouping circuit

Details Processor architecture including grouping circuit Processor architecture including grouping circuit

1997-03-31

2000-04-04

Maung, Zarni

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

712214, 712216, 712220, G06F 1500

Patent

active

060473681

ABSTRACT:
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture efficiently executes software code by providing the processor with a grouper circuit which receives software code instructions from a secondary memory and groups these instructions based upon the content of the instructions and provides these grouped instructions to the instruction cache of the processor. In this processor, the old instruction software code conforms to an old instruction set which is a subset of the new instruction set. Such a system also functions where the processor maps instructions to itself

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Siamak Arya, "A Mechanism For Hardware Compatibility For A New Architecture", Advanced Development Group, SPARC Technology Business, Sun Microsystems, Inc., pp. 1-5.

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