Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Patent
1997-12-29
1999-10-26
Vu, Viet D.
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
712 24, G06F 938
Patent
active
059745371
ABSTRACT:
A very long instruction word (VLIW) architecture describes a processor comprising multiple functional units operating in parallel. A very long instruction word contains a plurality of fields or issue slots for specifying which operations are to be performed by the functional units. Execution of an operation can be inhibited by a guard value specified in the issue slot. Instructions are dispatched in such a guarded VLIW architecture by routing one of a plurality of fields issued for a common functional unit based on the guard value. Thus, an instruction word may contain a greater number of issue slots than there are functional units.
REFERENCES:
patent: 5333280 (1994-07-01), Ishikawa
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5450556 (1995-09-01), Slavenburg et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5600810 (1997-02-01), Ohkami
patent: 5774737 (1998-06-01), Nakano
IEEE Comput. Soc. Press, "An Evaluation of the iHARP Multiple Instruction Issue Processor", Fleur L. Steven et al, pp. 437-444, 1994.
John R. Ellis, "Bulldog: A Cpmplier for VLIW Architectures", MIT Press 1985, ISBN 0-262-05034-X.
P. Y-T. Hsu, "Highly Concurrent Scalar Processing," Thesis, Univ. of Illinois at Urbana-Champaign, 1986.
Barschall Anne E.
Philips Electronics North America Corporation
Vu Viet D.
LandOfFree
Guard bits in a VLIW instruction control routing of operations t does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Guard bits in a VLIW instruction control routing of operations t, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Guard bits in a VLIW instruction control routing of operations t will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-776423