Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2008-07-15
2008-07-15
Bullock, Jr, Lewis A. (Department: 2195)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000, C718S103000
Reexamination Certificate
active
10424529
ABSTRACT:
Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the respective threads are used to determine the interleave frequency between the threads according to some instruction interleave rule. However, upon the occurrence of some predefined event or circumstance in the processor related to a particular instruction thread, the base input processing priority of one or more instruction threads is adjusted to produce one more adjusted priority values. The instruction interleave rule is then enforced according to the adjusted priority value or values together with any base input processing priority values that have not been subject to adjustment.
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Kalla Ronald Nick
Pham Minh Michelle Quy
Sinharoy Balaram
Ward, III John Wesley
Bullock, Jr Lewis A.
Culbertson Russell D.
Salys Casimer K.
The Culbertson Group P.C.
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