Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2006-11-28
2006-11-28
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S206000
Reexamination Certificate
active
07143268
ABSTRACT:
A data processor includes execution clusters, an instruction cache, an instruction issue unit, and alignment and dispersal circuitry. Each execution cluster includes an instruction execution pipeline having a number of processing stages, and each execution pipeline is a number of lanes wide. The processing stages execute instruction bundles, where each instruction bundle has one or more syllables. Each lane is capable of receiving one of the syllables of an instruction bundle. The instruction cache includes a number of cache lines. The instruction issue unit receives fetched cache lines and issues complete instruction bundles toward the execution clusters. The alignment and dispersal circuitry receives the complete instruction bundles from the instruction issue unit and routes each received complete instruction bundle to a correct one of the execution clusters. The complete instruction bundles are routed as a function of at least one address bit associated with each complete instruction bundle.
REFERENCES:
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5274818 (1993-12-01), Vasilevsky et al.
patent: 5502826 (1996-03-01), Vassiliadis et al.
patent: 5504932 (1996-04-01), Vassiliadis et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5732234 (1998-03-01), Vassiliadis et al.
patent: 5819058 (1998-10-01), Miller et al.
patent: 6029240 (2000-02-01), Blaner et al.
patent: 6079010 (2000-06-01), D'Arcy et al.
patent: 6167503 (2000-12-01), Jouppi
patent: 0 652 510 (1995-05-01), None
patent: 0 962 856 (1999-12-01), None
patent: WO 98/38791 (1998-09-01), None
patent: WO 99/19792 (1999-04-01), None
Chen, Crystal; Novick, Grege; and Shimano, Kirk. “Pipelining”. © 2000 pp. 1-5 http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/.
Chien. “Superscalar Execution”. © Feb. 29, 2000. Slides 6-10.
Brown Geoffrey M.
Faraboschi Paolo
Homewood Mark Owen
Jarvis Anthony X.
Vondran Gary L.
Chan Eddie
Hewlett-Packard Development Co. L.P.
Jorgenson Lisa K.
Li Aimee J.
Munck William A.
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