Floating point unit pipeline synchronized with processor...
Forcing regularity into a CISC instruction set by padding...
Functional-level instruction-set computer architecture for...
Fusing load and alu operations
Fusing load and alu operations
Fusion of processor micro-operations
Generating event signals for performance register control...
Handover between software and hardware accelerator
Hardware accelerator for a platform-independent code
High data density RISC processor
High performance adder for multiple parallel add operations
High speed, scalable microcode based instruction decoder for pro
Immediate and displacement extraction and decode mechanism
Implicitly derived register specifiers in a processor
Information processing apparatus and information processing...
Information processing apparatus provided with an optimized...
Inserting decoder reconfiguration instruction for routine...
Instruction code compression using instruction codes with...
Instruction code conversion apparatus creating an...
Instruction code conversion unit and information processing...