Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2001-02-07
2004-10-05
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S225000
Reexamination Certificate
active
06801996
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei12-30948 filed in Feb. 8, 2000 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to an instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit.
2. Prior Art
In the case where a microprocessor is implemented with fixed-length instruction codes (32-bit length in many cases) as RISC processors, the efficiency of coding tends to be low to increase the memory space for storing instruction codes as compared with a microprocessor implemented with variable-length instruction codes (8-bit to 32-bit length in many cases) such as CISC processors. The efficiency of coding used in this description is the ratio of the size of source codes to the size of the corresponding object codes as compiled.
It is difficult to employ such a processor requiring a higher capacity semiconductor memory chip or a number of memory chips for use in personal appliances. Although depending upon the architecture of the RISC processor, there are two main factors of lowering the efficiency of coding as follows.
(a) The length of the instruction codes is long such as the 32-bit fixed length.
(b) There are provided a small number of instructions.
In order to improve the efficiency of coding, with respect to the factor (a), there have been developed RISC processors implemented with fixed-length instruction codes of 16-bit lengths and RISC processors implemented with variable-length instruction codes of 16-bit/32-bit lengths. With respect to the factor (b), there have been developed RISC processors implemented with a variety of instructions comparable to a CISC processor. In the case of the processor with fixed-length instruction codes of 16-bit lengths, the factor (b) is not solved because the number of the available instructions is limited by the shorter bit length of the codes and because the immediate operands as treated are constrained (for example 16-bit data can not directly be manipulated), and therefore the efficiency of coding is not effectively improved. Also, since the number of instructions as required for the same program increases, the performance respective to the operation frequency tends to decrease as compared with a processor implemented with fixed-length 32-bit instruction codes.
RISC processors implemented with variable-length instruction codes of 16-bit/32-bit lengths have been developed to deal with these shortcomings. In this case, high speed operations are implemented with 32-bit instruction codes while the efficiency of coding is improved by providing a mixed sequence of 16-bit instruction codes and 32-bit instruction codes.
The additional instructions to be added to the instruction set of the existing processor include an instruction for switching the instruction mode (the mode in which are executed the original 32-bit instruction codes and the mode in which are executed the additional 16-bit instruction codes or a mixed sequence of 16-bit instruction codes and 32-bit instruction codes), and new instructions which are not corresponding to any 32-bit original instruction codes. For this reason, it is necessary to modify the hardware of the existing processor. For example, the existing processor has to be modified to provide an instruction code expanding circuit for expanding the additional instructions as compressed and an instruction decoding circuit for decoding the new instructions as introduced. Furthermore, it is necessary to modify some circuits inside of the processor such as the pipelined control circuit. The least significant bits of the program counter are used as a register to indicate the current instruction mode. The instruction code expanding circuit and the instruction decoding circuit are controlled with the register.
In the case of the RISC processors implemented with CISC-like complicated instructions, the instruction execution circuit becomes complicated so that it is difficult to enable high speed operations by increasing the operation frequency, which is the general feature of RISC processors. Accordingly, this kind of the processor has been designed to operate only at a relatively low speed (lower than 100 MHz).
On the other hand, several techniques have been proposed in order to improve the efficiency of coding as follows.
A first example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by modifying the compiler or the assembler for generating program codes. Generally, the source text of a target program is described in a high level language such as C-language and so forth. The compiler is used to convert the source text of a target program to an assembly source code program. The assembly source code program is converted into an object program consisting of instruction codes which are directly decoded by a processor. The number of steps is the number of instruction codes. The compiler or the assembler is modified in order that the source text of the target program is converted into a fewer number of instruction codes. On the other hand, in some processor, there are a plurality of the instruction codes having the same function. The assembler is modified in order that the source text of the target programis converted into instruction codes which have shorter code lengths. This function of the assembler is called optimization which can be refined to make shorter the instruction codes.
A second example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by adding new instructions to the processor. There are two cases in accordance with this technique. One is such that a single new instruction is introduced to indicate an operation which is accomplished by a plurality of existing instructions. The other is such that a new instruction is introduced to indicate an original instruction with a shorter code.
A third example is a modification of the second example. In accordance with the third example, additional instructions having shorter code lengths are introduced in order that each additional instruction is expanded to an original instruction respectively.
A fourth example is the techniques of generating an instruction code sequence which has a fewer number of steps or shorter code lengths by replacing original instructions of the processor by new instructions.
A fifth example is the techniques of compressing the entirety or part of a program composed of native instructions of the processor by a software and, when executed, the program as compressed is expanded by a software or a hardware. In accordance with the fifth example, it is possible to reduce the program memory as required in advance of execution on the basis of the ZIP algorithm, the LZH algorithm and so forth in the same manner as a file is compressed and expanded.
A sixth example is a modification of the fifth example. In accordance with the sixth example, a program composed of native instructions of the processor is divided into a plurality of blocks. Compression and expansion is performed for each block. The program as compressed is executed while expanding each block by a software or a hardware.
The technique in accordance with the first example has shortcomings that the limitation of the original instruction codes of the processor can not be overcome so that the efficiency of coding is improved only to the extent that the native instruction codes of the processor are effectively utilized. When further improvement becomes necessary, any of the second to sixth examples has to be employed. The technique in accordance with any of the second to fourth examples means that a new
Banno Moriyasu
Itaya Hiroshi
Saito Tomotaka
Shoda Tomoaki
Kabushiki Kaisha Toshiba
Tsai Henry W. H.
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