Instruction code compression using instruction codes with...

Details Instruction code compression using instruction codes with... Instruction code compression using instruction codes with...

2011-03-29

2011-03-29

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C710S068000

Reexamination Certificate

active

07917733

ABSTRACT:
An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands and having the same number of bits as the upper bit group. When 2N+1 (N is an integer of 1 or more) instruction codes having the same upper bit group continues in a series of instruction codes, respective reuse flags of the lower bit group of a 2n-th (n is an integer of 1 or more and N or less) instruction code and a (2n+1)-th instruction code in the series of instruction codes are set to “1”, and the lower bit groups of the 2n-th and (2n+1)-th instruction codes are integreted into one compressed instruction code.

REFERENCES:
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patent: 2007/0204133 (2007-08-01), Taniuchi
patent: 2004259234 (2004-09-01), None
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Fraser; An Instruction for Direct Interpretation of LZ77-compressed Programs; Sep. 2002.
Lin et al.; Code Compression by register operand dependency; Dec. 2003; Journal of Systems and Software 72, pp. 295-304.

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