Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...
Reexamination Certificate
2000-01-13
2003-07-01
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate variable length...
C712S223000, C712S300000, C712S224000, C707S793000
Reexamination Certificate
active
06587939
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to an information processing apparatus provided with an optimized executable instruction extracting unit for extending a compressed instruction into the corresponding executable instructions in accordance with the instruction code of a target executable program.
2. Description of the Related Art
In the field of control systems with embedded microcomputers, the size of instruction code in the memory of a processor can influence the production cost of the entire system. A smaller size of instruction code in the memory has an advantage in costs. The technique of compressing the executable instructions and extending the compressed instructions is one for techniques of reducing the size of instruction code in the memory.
In the case of the executable instructions, each instruction as pointed by an address register and fetched from the memory is latched by an instruction register and transferred to an instruction decoding unit through a multiplexer in order to decode the executable instructions.
On the other hand, in the case of the compressed instructions, each instruction as pointed by the address register and fetched from the memory is extended into the corresponding executable instructions and then transferred to the instruction decoding unit through the multiplexer in order to decode the executable instructions.
In accordance with “Intel Architecture Optimization Manual”, 1997, Intel Corporation, a “macro-instruction” stored in the instruction memory of the processor as discussed therein is generally extended into a plurality of corresponding “micro-ops”. Furthermore, in accordance with “TMS320C3x User's Guide”, 1997, TEXAS INSTRUMENTS, two instructions of “MPYI3” and “ADDIY3” for example are compressed as a compressed instruction “MPYI3| |ADDIY3” by imposing restrictions upon the usage such as the restrictions upon the usage the range of the register number available within the register field in the instruction format.
Such a compressed instruction of this kind is generated by compressing an instruction sequence which frequently occurs in the instruction codes of many application programs. However, in the actual case, there are a variety of application programs. Namely, while the compressed instruction set as defined by one processor is effective for a specific type of application program, it frequently becomes ineffective for another type of application program.
In order to improve the shortcomings, it has been contemplated to change the processor for the respective application program under question in order to make use of the compressed instruction set as optimized for the application program. However, it is ineffective to use different processors for different application programs. This is because the programmers are requested to understand the basic architecture of the processor and the software development environment each time as a new processor is employed. On the other hand, it is frequently the case that there is no processor available supporting the compressed instructions which a user desires. This is because many processors are designed in order to support the compressed instructions suitable for major application programs of which a substantial output of copies are expected.
As explained above, in the case of the prior art information processing apparatuses, the compressed instruction set is fixedly defined for each system. For this reason, while the compressed instruction set as defined in the system is effective for a specific type of application program, it becomes ineffective for another type of application program. In this case, there is the disadvantage that the use of compressed instructions can no longer improve the performance of the system.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an information processing apparatus having a compact storage region required of an executable program with a reduced number of instructions constituting the executable program.
Particularly, the information processing apparatus in accordance with the present invention is characterized by provision of a executable instruction extracting unit for extending a compressed instruction into a plurality of corresponding executable instructions, and a reconfiguration unit for reconfiguring and optimizing the executable instruction extracting unit suitable for the executable program.
In accordance with the present invention, the executable instruction extracting unit is reconfigured for the respective target program so that the number of the constituent instructions can be suppressed, resulting in compaction of the storage region for storing the target program.
REFERENCES:
patent: 4835679 (1989-05-01), Kida et al.
patent: 5717394 (1998-02-01), Schwartz et al.
patent: 5768597 (1998-06-01), Simm
patent: 5790874 (1998-08-01), Takano et al.
patent: 5819097 (1998-10-01), Brooks et al.
patent: 5838963 (1998-11-01), Griffiths
patent: 6131192 (2000-10-01), Henry
Intel Architecture Optimization Manual, Order No. 242816-003, Intel Corporation, 1997, pp. 1-2 through 3-35.
TMS320C3x, Digital Signal Processing Solutions, Texas Instruments, 1997, pp. 13-1 through 13-166.
Foley & Lardner
Kabushiki Kaisha Toshiba
Pan Daniel H.
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