Hardware accelerator for a platform-independent code

Details Hardware accelerator for a platform-independent code Hardware accelerator for a platform-independent code

2006-10-17

2006-10-17

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C717S136000

Reexamination Certificate

active

07124283

ABSTRACT:
The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4and P5are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

REFERENCES:
patent: 6775763 (2004-08-01), Sexton et al.
patent: 6820252 (2004-11-01), Sakamoto et al.
patent: 6826749 (2004-11-01), Patel et al.
patent: 6910205 (2005-06-01), Bak et al.
patent: 6910206 (2005-06-01), Nevill
patent: 1313012 (2003-05-01), None

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