Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2005-12-20
2010-10-05
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
C345S418000, C345S589000
Reexamination Certificate
active
07809928
ABSTRACT:
One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to receive the first event signal from the instruction parser, to select the first event signal from one or more event signals and to transmit the first event signal to an event logic block. The instruction decoder may be implemented in a multithreaded processing unit, such as a shader unit, and the occurrences of the first event signal may be tracked when one or more threads are executed within the processing unit. The resulting event signal count may provide a designer with a better understanding of the behavior of a program, such as a shader program, executed within the processing unit, thereby facilitating overall processing unit and program design.
REFERENCES:
patent: 3952304 (1976-04-01), Broniwitz et al.
patent: 5428749 (1995-06-01), Rouse et al.
patent: 5537541 (1996-07-01), Wibecan
patent: 5546037 (1996-08-01), Kenny et al.
patent: 5675729 (1997-10-01), Mehring
patent: 5796637 (1998-08-01), Glew et al.
patent: 5805850 (1998-09-01), Luick
patent: 5825674 (1998-10-01), Jackson
patent: 5835702 (1998-11-01), Levine et al.
patent: 5881223 (1999-03-01), Agrawal et al.
patent: 6006321 (1999-12-01), Abbott
patent: 6023759 (2000-02-01), Omtzigt
patent: 6067643 (2000-05-01), Omtzigt
patent: 6112318 (2000-08-01), Jouppi et al.
patent: 6356615 (2002-03-01), Coon et al.
patent: 6374367 (2002-04-01), Dean et al.
patent: 6775640 (2004-08-01), Swanson et al.
patent: 2002/0073255 (2002-06-01), Davidson et al.
patent: 2002/0124237 (2002-09-01), Sprunt et al.
patent: 2003/0126487 (2003-07-01), Soerensen et al.
patent: 2004/0006724 (2004-01-01), Lakshmanamurthy et al.
patent: 2005/0122334 (2005-06-01), Boyd et al.
patent: 2005/0188276 (2005-08-01), Hunter et al.
patent: 2006/0152509 (2006-07-01), Heirich
patent: 2007/0093986 (2007-04-01), Armstead et al.
Eggers, et al. “Simultaneous Multithreading: A Platform for Next-Generation Processors,” IEEE Micro, vol. 17, No. 5, pp. 12-19, Sep./Oct. 1997.
Allen Roger L.
Buck Ian A.
Coon Brett W.
Nickolls John R.
Chan Eddie P
NVIDIA Corporation
Partridge William B
Patterson & Sheridan LLP
LandOfFree
Generating event signals for performance register control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Generating event signals for performance register control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Generating event signals for performance register control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4240830