Electrical computers and digital processing systems: processing – Instruction decoding
Patent
1997-07-16
2000-04-11
Maung, Zarni
Electrical computers and digital processing systems: processing
Instruction decoding
712213, G06F 930
Patent
active
060498625
ABSTRACT:
A signal processor is disclosed having a program memory which stores compressed program instructions and a decoder device which decodes the compressed program instructions to form decoded program instructions for controlling functions of the signal processor. The decoder device has a programmable decoder and a fixed decoding arrangement, where the fixed decoding arrangement is non-programmable and hardwired for decoding the compressed program instructions using logical operations. The programmable decoder includes a decoder memory, such as a ROM or RAM, having cells for storing the decoded program instructions in an uncompressed form. These cells are addressed for executing programmable decoding functions of the programmable decoder. The compressed program instructions include a first number of bits for determining a category of the compressed program instructions and a second number of bits for determining the address of the cells. A control unit detects the category of the compressed program instructions and outputs a control signal to a multiplexer, which selectively connects the programmable decoder or the fixed decoding arrangement to the output of the signal processor.
REFERENCES:
patent: 3889242 (1975-06-01), Malmer, Jr.
patent: 4484268 (1984-11-01), Thoma et al.
patent: 4697250 (1987-09-01), Lee et al.
patent: 4992933 (1991-02-01), Taylor
patent: 5335331 (1994-08-01), Murao et al.
patent: 5408674 (1995-04-01), Norrie et al.
patent: 5568646 (1996-10-01), Jagger
patent: 5619665 (1997-04-01), Emma
patent: 5619714 (1997-04-01), Nishimura
patent: 5632024 (1997-05-01), Yajima et al.
patent: 5636352 (1997-06-01), Bealkowski et al.
patent: 5640248 (1997-06-01), Hirokawa
patent: 5652852 (1997-07-01), Yokota
patent: 5742781 (1998-04-01), Bajwa
patent: 5758115 (1998-05-01), Nevill
patent: 5768597 (1998-06-01), Simm
patent: 5784585 (1998-07-01), Denman
patent: 5787302 (1998-07-01), Hampapuram et al.
patent: 5794010 (1998-08-01), Worrell et al.
patent: 5826054 (1998-10-01), Jacobs et al.
patent: 5852741 (1998-12-01), Jacobs et al.
patent: 5867681 (1999-02-01), Worrell et al.
patent: 5870576 (1999-02-01), Faraboschi et al.
patent: 5878267 (1999-03-01), Hampapuram et al.
patent: 5884071 (1999-03-01), Kosaraju
patent: 5896519 (1999-04-01), Worrell
patent: 5922067 (1999-06-01), Nakayama
Bird, P., et al., "An Instruction Stream Compression Technique," CSE-TR-319-96, Univ. of Michigan, pp. 1-21, Nov. 1996.
Chen, I., et al., "The Impact of Instruction Compression on I-Cache Performance," CSE-TR-330-97, Univ. of Michigan, pp. 1-8, 1997.
Lefurgy, C., et al., "Improving Code Density Using Compression Techniques," CSE-TR-342-97, Univ. of Michigan, pp. 1-17, Jul. 1997.
Hennessy, J., et al., Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann, C1-26, Aug. 1995.
Opcode Remap and Compression in Hard Wired RISC Microprocessor, IBM TDB n10a 03-90, p. 349, Apr. 1993.
By IBM Technical Disclosure Bulletin, "Designing Flexibility into Hardwired Logic" vol. 37, Mar. 1, 1994, pp. 321-324.
Bauer Harald
Kempf Peter
Lorenz Dietmar
Meyer Peter
Caldwell Andrew
Halajian Dicran
Maung Zarni
U.S. Philips Corporation
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