Electrical computers and digital processing systems: processing – Instruction decoding – Decoding by plural parallel decoders
Patent
1997-12-19
2000-09-05
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding by plural parallel decoders
712215, 712204, G06F 930
Patent
active
061158070
ABSTRACT:
The invention, in one embodiment, is a static instruction decoder including a plurality of instruction inputs, a circular instruction queue, and an instruction rotator. The circular instruction queue is capable of receiving instructions from the instruction inputs, statically decoding the received instructions, indicating how many of the decoded instructions may issue in a next clock cycle, and outputting the decoded instructions in the next clock cycle, the number of instructions output being the number indicated. The instruction rotator is indexed by the indication of the circular instruction queue and points to the first instruction to issue in the next clock cycle.
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Ellis Richard L.
Intel Corporation
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