System and method for expanding the instruction set of an...

Details System and method for expanding the instruction set of an... System and method for expanding the instruction set of an...

2002-06-20

2010-11-09

Petranek, Jacob (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to generate an address of a microroutine

Reexamination Certificate

active

07831807

ABSTRACT:
A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch address. The branch address is then used to address a storage device such as a microcode RAM to retrieve one or more microcode instructions that control execution of the instruction opcode. Address generation is controlled by selecting a previously unused instruction opcode, then modifying the programmable bits as necessary to generate a desired branch address. By loading modified microcode instructions at the branch address, instruction execution can be modified without changing the hardware design.

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The Authoritative Dictionary of IEEE Standards Terms, 7thed. Standards Information Network IEEE Press, 2000. p. 765.

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