Single shared instruction predecoder for supporting multiple...

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component

Reexamination Certificate

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Reexamination Certificate

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07945763

ABSTRACT:
Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed with respect to each other. This cascaded delayed arrangement allows dependent instructions to be issued within a common issue group by scheduling them for execution in different pipelines to execute at different times.

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