Selective zero extension based on operand size

Details Selective zero extension based on operand size Selective zero extension based on operand size

2005-05-03

2005-05-03

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

C712S229000

Reexamination Certificate

active

06889312

ABSTRACT:
A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.

REFERENCES:
patent: 4868740 (1989-09-01), Kagimasa et al.
patent: 5091853 (1992-02-01), Watanabe et al.
patent: 5227989 (1993-07-01), Jones, Jr. et al.
patent: 5420992 (1995-05-01), Killian et al.
patent: 5758195 (1998-05-01), Balmer
patent: 5907694 (1999-05-01), Suzuki et al.
John L. Hennessy and David A. Patterson; Computer Architecture a Quantitative Approach; 1990; Morgan Kaufman Publishers, Inc.; 4th printing; p. 580.*
The Authoritative Dictionary of IEEE Standards Terms; 2000; IEEE Press; 7th Edition; p. 701.*
Intel Architecture Software Developer's Manual, vol. 1: Basic Architecture, Intel® Corporation, 1997, Chapter 3, pp. 5-7.
PowerPC™ Microprocessor Developer'Guide, © 1995 by Sams Publishing, pp. 42-44, 59-61.
The Technology Behind Crusoe™ Processors, Low-Power x86-Compatible Processors Implemented with Code Morphing™ Software, Transmeta Corporation, Jan. 2000, pp. 1-18.
Alpha Learns to Do Windows; Digital's FX!32 is The Key To Running Win32 Software on Alpha/Windows NT., Selinda Chiquoine, BYTE, Aug. 4, 1998, 4 pages.
Awards Stack Up for DIGITAL FX!32 Windows Compatibility Software for ALPHA, Digital Press Releases, Dec. 11, 199 7, 7 pages.
DIGITAL FX!32; White Paper: How DIGITAL FX!32 Works, DIGITAL Semiconductor, Jan. 26, 1998, 4 pages.
An Alpha in PC Clothing: Digital Equipment's New x86 Emulator Technology Makes An Alpha System a Fast x86 CloneTom Thompson, BYTE, Aug. 4, 1998, 7 pages.
ADM 64-Bit Technology; The AMD x86 Architecture Programmers Overview, AMD, Publication #24108 Rev: A, Aug. 2000, pp. 1-106.
AMD 64-Bit Technology; The AMD x86-64 Architecture Programmers Overview, AMD, Pulication #24108 Rev: C, Jan. 2001, pp. 1-128.
Office Action mailed Jun. 18, 2003 from U.S. Appl. No. 09/596,867, 8 pages.

Affiliated with

Also associated with

Rating

Selective zero extension based on operand size does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Selective zero extension based on operand size, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective zero extension based on operand size will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3375457