Status register update logic optimization

Details Status register update logic optimization Status register update logic optimization

2006-10-31

2006-10-31

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

C712S219000

Reexamination Certificate

active

07130988

ABSTRACT:
A system and method for handling a status change in a pipeline microprocessor. The pipeline microprocessor determines, at the decode unit, if an instruction is a status instruction. If the instruction is determined to be a status instruction, the decode unit delays the start of the following instruction a sufficient number of clock cycles to allow the status change to propagate through the system pipeline.

REFERENCES:
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patent: 5751985 (1998-05-01), Shen et al.
patent: 5815698 (1998-09-01), Holmann et al.
patent: 6304955 (2001-10-01), Arora
patent: 2002/0069348 (2002-06-01), Roth et al.
Massey “Pipeline Hazards” pp. 1-6—http://cs-alb-pc3.massey.ac.nz
otes/59304/113.html.

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