Predicting a sequence of variable instruction lengths from previ

Details Predicting a sequence of variable instruction lengths from previ Predicting a sequence of variable instruction lengths from previ

1997-12-18

2000-09-26

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate variable length...

712204, 712213, G06F 938

Patent

active

06125441&

ABSTRACT:
An instruction cache having a pattern detector for use in predicting the length of variable length instructions in a microprocessor. The instruction cache comprises an instruction length calculation unit and the pattern detector. The pattern detector is configured with a content addressable memory and update logic. The content addressable memory stores fetch addresses and instruction lengths calculated by the calculation unit. The content addressable memory compares particular fetch addresses that it receives with fetch addresses already stored and outputs corresponding predicted instruction length sequences. The content addressable memory may receive, compare, and store instruction lengths or instruction bytes in addition to, or in lieu of, fetch addresses. A neural network or other type of memory configuration may be used in place of the content addressable memory.

REFERENCES:
patent: 5488710 (1996-01-01), Sato et al.
patent: 5513330 (1996-04-01), Stiles
patent: 5689672 (1997-11-01), Witt et al.
patent: 5724422 (1998-03-01), Shang et al.
patent: 5748978 (1998-05-01), Narayan et al.
patent: 5751981 (1998-05-01), Witt et al.

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