Electrical computers and digital processing systems: processing – Instruction decoding
Reexamination Certificate
2009-04-03
2011-12-13
Faherty, Corey (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Reexamination Certificate
active
08078841
ABSTRACT:
An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general register, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.
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Ehrman John R.
Greiner Dan F.
Chiu, Esq. Steven
Faherty Corey
Heslin Rothenberg Farley & & Mesiti P.C.
International Business Machines - Corporation
Schiller, Esq. Blanche E.
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