Parallel subword instructions with distributed results

Details Parallel subword instructions with distributed results Parallel subword instructions with distributed results

2002-03-30

2008-10-21

Pan, Daniel (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Predecoding of instruction component

C712S300000

Reexamination Certificate

active

07441104

ABSTRACT:
The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the parallel subword compare operations can be stored at that bit position within the respective subword location of a result register. Alternatively, for a shifting-type instruction, pre-existing contents of a result register can be shifted one bit toward greater significance while the results are of the present operation are stored in the least-significant bits of respective result-register subword locations. This approach provides the results of multiple parallel subword compare instructions to be combined with relatively few instructions and reduces the maximum lateral movement of information—both of which can enhance performance.

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patent: WO00/22511 (2000-04-01), None

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