Processor adapted to receive different instruction sets

Details Processor adapted to receive different instruction sets Processor adapted to receive different instruction sets

2005-06-08

2008-09-23

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

Reexamination Certificate

active

07428630

ABSTRACT:
A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1:i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation.A first operation (add) is specifiable in both the first and second external formats (F1, F2), and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical.Such “congruent” instruction encodings can enable a translation process, for translating the external-format opcode into a corresponding internal-format opcode, without the need to positively identify each individual external-format opcode.

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