Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
Patent
1998-09-11
2000-03-14
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to generate an address of a microroutine
712711, 712 18, 712 25, 712200, 712201, G06F 1500
Patent
active
060386568
ABSTRACT:
An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.
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Cummings Uri V.
Lines Andrew M.
Martin Alain J.
An Meng-Ai T.
California Institute of Technology
Whitmore Stacy
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