Device and method for processing instructions based on...
Different register data indicators for each of a plurality...
Digital signal processor computation core with pipeline...
Digital signal processor having distributed register file
Dual-target block register allocation
Dynamic concurrent atomic execution
Dynamic data dependence tracking and its application to...
Dynamic instruction dependency monitor and control system
Dynamic instruction dependency monitor and control system
Dynamic recalculation of resource vector at issue queue for...
Dynamic recalculation of resource vector at issue queue for...
Dynamically reconfigurable stages pipelined datapath with...
Dynamically reconfigurable stages pipelined datapath with...
Dynamically shared group completion table between multiple...
Dynamically typed register architecture
Early condition code evaluation at pipeline stages...
Early data return indication mechanism
Early data return indication mechanism for data cache to...
Early exit processing of iterative refinement algorithm...
Early exit processing of iterative refinement algorithm...