Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2006-09-28
2008-11-11
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C710S036000, C711S154000, C711S118000, C711S122000, C713S502000
Reexamination Certificate
active
07451295
ABSTRACT:
One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.
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Domen Stanley J.
Hinton Glenn
Kuttanna Belliappa
Milstrey Robert G.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kim Hong
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