Dynamically reconfigurable stages pipelined datapath with...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble

Reexamination Certificate

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C712S225000

Reexamination Certificate

active

11229616

ABSTRACT:
A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiplexers in the pipeline circuit. In other words, when a valid datum is being processed, the pipeline register is activated to latch the output of the combinational logic circuit; otherwise, when an invalid datum is received, the register is not activated and the datum bypasses the register through a multiplexer. Therefore, the pipeline stages of the pipelined datapath are dynamically reconfigured to save the power dissipation effectively.

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Thucydides Xanthopoulos, et al., “A Low-Power IDCT Macrocell for MPEG-2 MP @ ML Exploiting Data Distribution Properties for Minimal Activity”, IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999.
Suhwan Kim, et al., “Reconfigurable Low Energy Multiplier for Multimedia System Design”, downloaded from internet URL portal.acm.org/citation.cfm?id=838111 on Aug. 23, 2005, IEEE Computer Society Annual Workshop on VLSI, p. 129, Apr. 27, 2000.

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